A FPGA-Based Post-Processing and Validation Platform for Random Number Generators

Computer security relies heavily on random numbers (RN) for key exchange of authentication algorithms. However, IoT device security is often based on poor quality PRNGs. This issue can be overcome using TRNGs that may offer better quality and higher security. Nonetheless, TRNG sources often provide slow throughput and require post-processing to correct hardware biases and ensure the desired statistical behavior. We propose a FPGA-based hardware platform able to validate and post-process multiple TRNG sources. A provably secure post-processing algorithm (SPRG) is implemented in hardware. This algorithm improves RN quality while maintaining high throughput. A platform providing hardware acceleration has been implemented on a Kintex-7 FPGA board. It tests the validity of the generated numbers through X² and SP800-90B online statistical tests and improves the bitstream randomness by using AIS-31 or SPRG post-processing hardware cores. The platform is modular and targets both back-end servers and IoT edge devices.

    Organizational unit
    HERVA
    Type
    Dataset
    DOI
    10.26037/yareta:pbdtwm7tzbh63iwcxb4gwaslhq
    License
    Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International
Publication date24/01/2020
Retention date21/01/2030
accessLevelPublicAccess levelPublic
SensitivityUndefined
duaNoneContract on the use of data
Contributors
  • Duc, Alexandre
  • Glück, Florent orcid
  • Vannel, Fabien
  • Steiner, Lucie
  • Upegui, Andres
  • Gantel, Laurent
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HERVA
A FPGA-Based Post-Processing and Validation Platform for Random Number Generators
2020 accessLevelPublic Public 279.1 KB
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